Exemplary embodiments of the present invention relate to a semiconductor device fabrication technology, and more particularly, to a nonvolatile memory device having a single polysilicon floating gate.
In order to implement lightweight and slim systems, research into system on a chip (SoC) has been actively conducted to implement organic operations between a plurality of integrated semiconductor devices. An SoC may be configured by integrating a logic device (e.g., a display device IC (DDI)) and a nonvolatile memory device into a single chip. In the SoC in which the logic device and the nonvolatile memory device are integrated, various types of nonvolatile memory device may be applied, and a suitable nonvolatile memory device is selected according to the purpose of the chip and configuration of the logic device.
As a nonvolatile memory device applied to an SoC, a single gate type multi-time programmable (MTP) or a stack gate type sidewall selective transistor cell (SSTC) is widely used.
However, a typical MTP which uses a hot electron injection in a program operation and uses a Fowler-Nordheim (F-N) tunneling in an erase operation is advantageous in that it can be fabricated by adding about two mask processes to a logic operation, but is disadvantageous in that a size of a unit cell is too large.
On the other hand, the SSTC which uses an F-N tunneling in a program operation and an erase operation is advantageous in that a size of a unit cell is so small that the degree of integration of an SoC can be improved, but is disadvantageous in that fabrication cost and time are increased because its structure is complicated and about 10 mask processes are added.